Our paper presented at the International Workshop on Smalltalk Technology 2015, Brescia Italy, as part of the PhD of LE Xuan Sang received the 1st prize, offered by the Lam Research Corporation.

A Meta Model Supporting Both Hardware and Smalltalk-based Execution of Fpga Circuits
High level synthesis (HLS) refers to an automated process that creates a digital hardware from an algorithmic description of some computation. From the perspective of Smalltalk, this process consists in converting a code from the OO level to the register transfer level (RTL), that supports direct compilation to the hardware level. In this paper, we present first steps to achieve this process. We introduce a Smalltalk-based meta-model that allows to express descriptions (i.e. models) of digital circuits. These descriptions materialize as Smalltalk code. A such circuit description can be run on top of the Smalltalk VM, simulating the parallelism intrinsic to hardware. Alternatively, it can be compiled into a binary representation directly transferable to FPGA chips, which can run and exchange data with Smalltalk objects.

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